--
-- VHDL Architecture Fietscomputer_lib.gen_multiplier.combi
--
-- Created:
--          by - jcmooije.UNKNOWN (dtp7985)
--          at - 16:49:17  7-07-2010
--
-- using Mentor Graphics HDL Designer(TM) 2007.1 (Build 19)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

ENTITY fc_15_to_63 IS

  PORT( 
  BCD   : IN     STD_LOGIC_VECTOR(15 DOWNTO 0);
  uit   : OUT     STD_LOGIC_VECTOR(63 DOWNTO 0)
  );
  
  
END fc_15_to_63 ;


ARCHITECTURE combi OF fc_15_to_63 IS




BEGIN
  
  
  uit <= EXT(BCD,64);
    
  
   
    
  END ARCHITECTURE combi;
  
  
  
  
  